1. Field of the Invention
The present invention relates generally to electronic devices and methods of manufacturing the same. In particular, the present invention relates to an electronic device including a first semiconductor device and a second semiconductor device electrically connected to the first semiconductor device, where the first semiconductor device includes a first electronic component and a first multilayer interconnection structure electrically connected to the first electronic component and the second semiconductor device includes a second electronic component and a second multilayer interconnection structure electrically connected to the second electronic component.
2. Description of the Related Art
FIG. 1 is a cross-sectional view of a conventional electronic device 200.
Referring to FIG. 1, the conventional electronic device 200 includes a first semiconductor device 201, a second semiconductor device 202, and internal connection terminals 203. The first semiconductor device 201 includes a wiring board 211 (a first multilayer interconnection structure), a first electronic component 212, underfill resin 213, and external connection terminals 214.
The wiring board 211 is a plate-shaped multilayer interconnection structure. The wiring board 211 includes stacked insulating layers 216 and 217; interconnection patterns 219, 228, and 229; pads 221; solder resist layers 222 and 226; and external connection pads 223 and 224. The insulating layer 216 is provided on an upper surface 217A of the insulating layer 217.
The interconnection patterns 219 and the pads 221 are provided on an upper surface 216A of the insulating layer 216. The interconnection patterns 219 include pad parts 232 and 233, which are not covered with the solder resist layer 222 and are exposed. The pads 221 are not covered with the solder resist layer 222 and are exposed.
The solder resist layer 222 is provided on the upper surface 216A of the insulating layer 216. The external connection pads 223 and 224 are provided on a lower surface 217B of the insulating layer 217. The lower surfaces of the external connection pads 223 and 224 are not covered with the solder resist layer 226 and are exposed.
The solder resist layer 226 is provided on the lower surface 217B of the insulating layer 217. The interconnection patterns 228 and 229 are provided inside the stacked insulating layers 216 and 217. The interconnection patterns 228 are connected to the corresponding pad parts 233 and external connection pads 223. The interconnection patterns 229 are connected to the corresponding pads 221 and external connection pads 224.
The first electronic component 212 is placed between the first semiconductor device 201 and the second semiconductor device 202. The first electronic component 212 includes electrode pads 236. The electrode pads 236 are electrically connected to the corresponding pad parts 232 through bumps 237 (for example, solder bumps).
The underfill resin 213 is provided to fill in the gap between the first electronic component 212 and the wiring board 211. The external connection terminals 214 are provided on the lower surfaces of the corresponding external connection pads 223 and 224.
The second semiconductor device 202 is provided over the first semiconductor device 201. The second semiconductor device 202 includes a wiring board 241 (a second multilayer interconnection structure), a second electronic component 243, and molded resin 246. The wiring board 241 has a plate shape, and includes pads 251, 252 and 254. The pads 251 face the pad parts 233, and are electrically connected to the pad parts 233 through the corresponding internal connection terminals 203. The pads 252 face the pads 221, and are electrically connected to the pads 221 through the corresponding internal connection terminals 203. The pads 254 are electrically connected to the pads 251 or the pads 252.
The second electronic component 243 is bonded onto the wiring board 241, and is electrically connected to the pads 254 through metal wires 244. The molded resin 246 is provided on the wiring board 241. The molded resin 246 seals the metal wires 244 and the second electronic component 243.
The diameter (height) of the internal connection terminals 203 is determined so that the first electronic component 212 and the second semiconductor device 202 are out of contact with each other. The internal connection terminals 203 may have a height of, for example, 200 μm. (See, for example, Japanese Laid-Open Patent Application No. 6-13541.)